1. Field of the Invention
The present invention relates to system-on-a-chip architecture . More particularly, the present invention relates to an field programmable gate array and a microcontroller in a system-on-a-chip architecture.
2. The Background Art
An integrated circuit uses a network of metal interconnects between individual semiconductor components which are patterned with standard photolithographic processes during wafer fabrication. Multiple levels of metallized patterns may be used to increase the flexibility of the interconnects.
It has long been recognized that a user-programmable interconnect technique would allow lower tooling costs, and faster delivery time. To such an end, field programmable gate array (FPGA) circuits were developed. An FPGA is an array of uncommitted gates with uncommitted wiring channels. To implement a particular circuit function, the circuit is mapped into the array and the wiring channels and appropriate connections are programmed to implement the necessary wiring connections that form the circuit function.
A gate array circuit can be programmed to implement virtually any set of functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from the user""s system, through input buffers, then through the circuit, and finally back out to the user""s system via output buffers. Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation, or hysteresis.
There are essentially two configurations of programmable circuit elements used to provide flexibility to the user for programming the FPGA. In the first configuration, example of which is disclosed by El Gamal, et al. in U.S. Pat. No. 4,758,745, the FPGA can be permanently programmed by the user. In the second configuration, an example of which is disclosed by Freeman in U.S. Pat. No. 4,870,302, the FPGA can be changeably programmed by the user.
An application-specific integrated circuit (ASIC), such as a microcontroller is a mask-programmable gate array offers higher functionality and performance and more efficient use of space than an FPGA which offers lower design costs and greater user flexibility. Also, an ASIC can implement any variety of I/O function and often at a higher speed than an FPGA. Other dedicated functional circuitry may also offer higher functionality and performance than its equivalent configured from FPGA components.
In a system-on-a-chip (SOC) with both an FPGA and an ASIC portion provides some portion of the advantages of both designs. Of major concern in designing an SOC is providing a suitable interface between the FPGA and ASIC portions. In order for the IC to perform its tasks properly, the FPGA and ASIC portions must be able to communicate effectively with each other.
In the present invention, an FPGA core tile may be employed as a stand alone FPGA, repeated in a rectangular array of core tiles, or included with other devices in a system-on-a-chip (SOC). The core tile includes a rectangular array of logic clusters, a column of random access memory (RAM) modules, and I/O clusters. Horizontal and vertical routing channels as well as clocking resources provide interconnection between the logic clusters, the RAM modules and the I/O clusters.
The horizontal routing resources include a horizontal routing channel, output routing tracks, and horizontal highway routing channels. The vertical routing resources include vertical routing channel and vertical highway routing channels. The horizontal routing channels and vertical routing channels each include sub-channels having various numbers of tracks, and are segmented with programmable elements at various lengths. Each of the horizontal and vertical highway routing channels spans the entire length of a core tile. The clocking resources include routed and hardwired clocks that run the width and length of a core tile, respectively.
The horizontal routing resources and routed clock pairs extend into the columns of I/O clusters and the RAM modules, and the vertical routing resources and hardwired clocks extend into the rows of I/O clusters. Each of the columns of I/O clusters and RAM modules have their own vertical routing resources and hardwired clocks, and each of the rows of I/O clusters have their own horizontal routing resources, routed clock. Included at the uppermost edge of the rows of logic clusters is a channel that includes a horizontal routing channel and a routed clock pair. Programmable connections are provided by programmable elements between the routing resources. Preferably, the programmable elements are antifuses.
The unit of segment length for the horizontal routing channel is one-half a column of logic clusters, and the tracks in the horizontal routing channel are segmented in a pattern that repeats itself in every column of logic clusters. The unit of segment length for the vertical routing channel is one row of logic clusters, and the tracks in the vertical routing channel are segmented in a pattern which repeats itself after every two rows of logic clusters.
A logic cluster includes logic modules, flip-flop modules, a buffer module, transmitter modules, and receiver modules. A logic module is a combinatorial logic unit and includes first, second, third and fourth multiplexors each having first and second data inputs, an output, and a select input. A FF module is sequential logic unit that includes a four-input multiplexor having first and second select inputs, first, second, and three two-input multiplexors having a single select input, and a D-type flip-flop. The buffer, transmitter and receiver modules include buffers that may be programmably to connected routing resources.
The RAM blocks are dual ported for simultaneous read and write operations and may be configured as 128 36-bit wide words, 256 18-bit wide words, 512 9-bit wide words, 1K for 4-bit wide words, or 4K 1-bit wide words. The RAM blocks can be selected to include collision detection and parity generation and check, and may be synchronous or asynchronous.
An I/O cluster includes I/O modules, a buffer module, transmitter modules, and receiver modules. The I/O module includes a FIFO, an input flip-flop, an output flip-flop, and an enable flip-flop, and is coupled to an I/O pad, by a boundary scan register module and input and output buffers. The I/O pad may be programmed with different options by an I/O options module. The input flip-flop, an output flip-flop, and an enable flip-flop include a four-input multiplexor, first, second and third two-input multiplexors and a D-type flip-flop.
An LVDS core can be employed to input and output signals between the I/O pads and a FIFO. The LVDS core includes circuits for receiving data, and circuits for transmitting data.
In another aspect of the present invention a system on a chip (SOC) architecture includes an FPGA core tile and associated virtual component interface (VCI) logic, a micro-controller and associated VCI logic, external interface circuits JTAG and UART and associated VCI logic and, respectively, and system/peripheral bus and bridge and associated VCI logic.
The VCI logic associated with various components is designed to translate the signals of each of the components with which they are associated into universal signals that form a standard protocol which is understood by the remaining components in the SOC. Communication of the signals from a first component to a second component requires that certain of the signals from the first component be first translated to universal signals by the VCI associated with the first component. These universal signals are the translated by the VCI associated by the second component to signals on which the second component normally operates. Others of the signals from a first component will be directly connected to the second component. When the system/peripheral bus is employed in the communication of translated signals from a first component to a second component using a bus, the communication may also require translation of the universal signals onto and off of the system/peripheral bus.